Output list
Book chapter
Implementing NChooseK on IBM Q Quantum Computer Systems
Published 05/23/2019
Reversible Computation, 209 - 223
This work contributes a generalized model for quantum computation called NChooseK. NChooseK is based on a single parametrized primitive suitable to express a variety of problems that cannot be solved efficiently using classical computers but may admit an efficient quantum solution. We implement a code generator that, given arbitrary parameters for N and K, generates code suitable for execution on IBM Q quantum hardware. We assess the performance of the code generator, limitations in the size of circuit depth and number of gates, and propose optimizations. We identify future work to improve efficiency and applicability of the NChooseK model.
Book chapter
A Survey of Programming Tools for D-Wave Quantum-Annealing Processors
Published 05/29/2018
High Performance Computing, 103 - 122
The rapid growth in the realized performance of D-Wave Systems’ annealing-based quantum processing units (QPUs) has sparked a surge in tools development to deliver the anticipated performance to application developers. In this survey we describe the tools that are available, their goals (e.g., performance or ease of use), the programming abstractions they expose, and their use for application development. The existing tools confirm the need for interfaces at a variety of points on the continuum between complexity and simplicity in using the QPU. Most of the current tools abstract the hardware’s native topology but generally not using existing interfaces that are familiar to typical programmers. To date, only a small number of applications have been implemented for QPUs. Our survey finds that tools provide potentially great leverage to enable more applications as long as the tools expose the appropriate abstractions and deliver the anticipated performance.
Book chapter
High Performance Interconnects for Massively Parallel Sys- tems
Published 2010
Attaining High Performance Communications, 33 - 56
If you were intent on building the world’s fastest supercomputer, how would you design the interconnection network? As with any architectural endeavor, there are a suite of trade-offs and design decisions that need to be considered:Maximize performance Ideally, every application should run fast, but would it be acceptable for a smaller set of “important” applications or application classes to run fast? If so, is the overall performance of those applications dominated by communication performance? Do those applications use a known communication pattern that the network can optimize?